With development in the electronic industry, electronic products have been developed toward providing multiple functions and high performances. In order to achieve high integration and size miniaturization of a semiconductor package, a circuit board for carrying multiple active/passive components and circuits has evolved from a double-layer board to a multi-layer board, wherein an available circuit area of the multi-layer circuit board is enlarged via interlayer connection technology within a limited space for accommodating integrated circuits with a high circuit density.
Moreover, due to an increase in popularity of portable products such as communication, network and computer products etc., BGA (ball grid array) packages, flip-chip packages, CSPs (chip size packages) and MCM (multi chip module) packages have become mainstream products in the market as they are incorporated with size-reduced integrated circuits (ICs) and have a high density and a large number of leads or input/output (I/O) connections. These packages are usually cooperative with high capability chips such as microprocessors, chip modules and graphics chips etc. to achieve higher speed operation. However, fabrication limitations of an IC package substrate with circuits on the functions thereof, such as chip signal transmission, bandwidth improvement and control resistance, impede the use of such substrate in a package with a large number of I/O connections. As the package size is reduced to approximately the chip size, bow to develop a package substrate with fine circuits and a high density of fine vias is an important research task.
Accordingly, a conventional method for fabricating a multi-layer circuit board by using build-up technology has been provided. FIGS. 1A to 1D show a build-up method for fabricating a multi-layer circuit board, and this build-up method generally includes two steps: preparing a core and performing a circuit build-up process. Referring to FIG. 1A, first, a core 11 is prepared, which comprises a resin core layer 111 with a pre-determined thickness and circuits 112 formed on front and back surfaces of the resin core layer 111. A plurality of plated through holes 113 are formed in the resin core layer 111 to electrically connect the circuits 112 on the front and back surfaces of the resin core layer 111. Then referring to FIG. 1B, a build-up process is performed on the core 11 to form a dielectric resin layer 12 on the front and back surfaces thereof respectively, and the dielectric resin layer 12 is provided with a plurality of blind vias 13 for exposing portions of the circuits 112. Referring to FIG. 1C, a metal conductive film 14 is deposited on an exposed surface of the dielectric resin layer 12, side walls of the blind vias 13 and the exposed portions of the circuits 112 by means of an electroless plating or sputtering technique, and a patterned dry film 15 is formed on the metal conductive film 14. The patterned dry film 15 has a plurality of openings 150 for exposing portions of the conductive film 14 on which a patterned circuit layer is to be formed. Finally referring to FIG. 1D, a patterned circuit layer 16 is formed in the openings 150 of the dry film 15 by an electroplating technique, wherein the patterned circuit layer 16 is electrically connected to the circuits 112 through the blind vias 13, and then the dry film 15 and the part of the conductive film 14 covered by the dry film 15 are removed by etching, such that a build-up structure 10a is fabricated on each of the front and back surfaces of the core 11 so as to achieve a 1+2+1 substrate 10 with multi-layer circuitry (i.e. 2 build-up structures and a double-layer core). Similarly, the above build-up process may be repeated to form a second build-up structure on the build-up layer 10a (referred to as “first build-up structure”) so as to fabricate a 2+2+2 substrate with multi-layer circuitry. Related prior arts include U.S. Pat. Nos. 5,837,427, 5,994,771 and 6,384,344.
Subsequently, BGA semiconductor packaging processes are readily performed, which allow a semiconductor chip to be mounted on a front surface of the foregoing substrate with desirable circuitry, and allow a plurality of solder balls to be implanted on a back surface of the substrate, wherein the solder balls are used to electrically connect the BGA package to an external electronic device such as printed circuit board (PCB). In order to reduce the weight and size of electronic products, there is provided a TFBGA (thin and fine ball grid array) package having a smaller overall size than the conventional BGA package. The TFBGA packages are normally fabricated in a batch manner on a substrate strip, wherein the substrate strip is predefined with a plurality of package sites each for forming a single TFBGA package. A singulation process is finally performed to separate apart the plurality of package sites to form a plurality of individual TFBGA packages.
Generally to provide electrical connection and bonding of a semiconductor package to an external electronic device (such as PCB) via solder balls, or provide efficient electrical connection of a semiconductor chip to a substrate, a plurality of conductive traces such as copper traces are formed on surfaces of the substrate and extended to form connecting pads where a nickel/gold metal layer is applied to allow conductive elements, such as gold wires, bumps or solder balls to be effectively bonded to the connecting pads of the substrate and electrically connect the substrate to the chip or PCB, and also to prevent the connecting pads from oxidization due to external environmental influences. For forming the nickel/gold metal layer having high electrical conductivity, during the fabrication of the substrate, the connecting pads are adapted to be electrically connected to a plating bus, such that a plating current can go through the plating bus to the connecting pads and allow the nickel/gold metal layer to be deposited on the connecting pads. When the semiconductor package is fabricated, the plating bus becomes useless and is removed.
A layout method of the TFBGA substrate is shown as FIG. 2. The TFBGA substrate 200 is divided into a plurality of substrate units 20 by a plurality of transverse cutting lines SLx and a plurality of longitudinal cutting lines SLy. The substrate units 20 serve as package sites to be subjected to subsequent packaging processes and would be separated from each other by means of a final singulation process cutting along the cutting lines SLx and SLy. A circuit layout of each substrate unit 20 includes a plurality of bonding pads 21, a plurality of conductive through holes 22, and a plurality of conductive traces 23 electrically connected to the bonding pads 21 and the conductive through holes 22. The conductive through holes 22 are used to electrically connect the conductive traces 23 on a front surface of the substrate unit 20 to ball pads (not shown) on a back surface of the substrate unit 20. In order to electroplate a nickel/gold metal layer on the bonding pads 21 on the front surface and the ball pads on the back surface of the substrate unit 20, the conductive through holes 22 are adapted to be electrically connected to a plating bus 24 formed around each substrate unit 20, so that a plating current can go through the plating bus 24 to all the conductive through holes 22 and then to the bonding pads 21 and the ball pads of the substrate unit 20. The plating bus 24 is formed in a grid shape and located on the cutting lines SLx and SLy, such that the plating bus 24 can be removed during the final singulation process. Related prior arts include U.S. Pat. Nos. 6,281,047, 6,319,750 and 6,479,894.
However, the above layout method for the substrate has a plurality of drawbacks. Since the plating bus is formed around the substrate units, before the substrate units are singulated, electrical tests cannot be performed on the substrate units. As a result, if inner-layer circuits of the substrate units generally for signal connection and grounding or powering purposes are incurred with defective appearance during the substrate fabrication, this situation would not be realized, and such substrate units would still be subjected to subsequent die-bonding and packaging processes if the substrate units have good outer-layer circuits and bonding pads or ball pads. This not only causes a waste of materials and cost but also leads to an increase in fabrication steps and time, as well as sacrifices the client's good dies due to fabrication of products with defective inner-layer circuits as it is incapable of detecting failure of the inner-layer circuits at an earlier stage.
Therefore, the problem to be solved here is to provide a method for indicating whether inner-layer circuits of a substrate are good and thus indicating whether the substrate should be subjected to subsequent packaging processes, so as to prevent a waste of materials and cost, an increase in fabrication steps and time, and sacrifice of the client's good dies from occurrence.